This invention relates to correlators for determining the degree of coincidence between two signals. More particularly this invention relates to digital time compression correlators and even more specifically to time compression correlators which determine the degree of coincidence between two signals as a function of a time delay introduced between them by causing one of the signals to be subjected to an indexed timed delay while comparing it to the other signal.
Time compression correlators using shift registers as the delay device have had the general design illustrated in FIG. 1. The three registers are designated Moving Time Series 1 (MTS 1), Moving Time Series 2 (MTS 2), and Stationary Time Series (STS). Two registers, MTS 1 and MTS 2, accumulate consecutive data samples of two waveforms and generate high-frequency replicas of these waveforms. The STS accepts the output of MTS 2 and generates a high-frequency replica of these data. The STS operation differs from MTS operation in that the MTS accumulates one data sample and drops one previously accumulated data sample during each sample period. In the STS, all data are replaced in the shift registers during one sample period. The coincidence logic compares the output of the STS and MTS 1 to generate an output corresponding to the degree of correlation between the inputs of MTS 1 and MTS 2. For this circuit, data are sampled at fs Hz, and the data in each register shift at N times fs Hz, where N is the length of the stationary time series.
Generally, ordnance systems dictate the shift register length and sample frequency. Since these parameters determine the clock frequency, power dissipation cannot be reduced by restricting the highest allowable clock frequency without some information loss. When an application requires large shift registers, the clock frequency, and thus power dissipation, increases significantly making this design impractical for battery operation for long periods.